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12-bit, 170/210 msps 3.3 v a/d converter ad9430 rev. c in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features snr = 65 db @ f in = 70 m hz @ 210 msps enob of 10.6 @ f in = 70 mhz @ 210 msps (C 0.5 dbfs) sfdr = 80 db c @ f in = 70 mh z @ 21 0 msps (C 0.5 dbfs) excellent linea r ity: dnl = 0.3 lsb (typical) inl = 0.5 lsb (typical) 2 output data options: demultipl e xed 3.3 v cmos ou tputs each @ 1 05 msps interleave d or parallel data o u tput option lvds at 210 m s ps 700 mh z fu ll-p o wer analog bandwidth on-chip reference and track-a nd-hold power dissipati o n = 1.3 w typi cal @ 2 10 msps 1.5 v input volt age range 3.3 v supply op eration output data format option data s y nc input and data clock output provi d ed clock du ty cy cle stabilizer applic ati o ns wireless and w i red bro a dban d co mmunicatio n s cable re verse path communications test eq uipm ent radar an d sate llite s u bsystem s power amplifie r linearization general description the ad9430 is a 12-b i t m o n o li t h ic s a m p l i n g a n alog-t o-dig i t a l co n v er t e r o p timize d f o r high p e r f o r ma n c e , lo w p o w e r , an d ease o f us e . the p r o d uc t o p er a t es u p t o a 210 ms p s co n v ersio n r a te a nd is o p t i mi ze d fo r o u tst a n d ing d y na mic p e r f o r ma n c e in wi deb a n d ca r r i e r a n d b r o a d b and sy stem s. al l ne cess a r y f u n c t i o n s, i n cl u d in g a t r ack - and- h o ld (t /h) and r e fer e n c e, a r e in cl ude d o n t h e c h i p t o p r o v ide a co m p lete con v ersio n s o l u tion. the ad c r e q u i r es a 3.3 v p o wer s u p p l y a nd a dif f er en t i al en c o d e clo c k fo r f u l l p e r f o r ma n c e o p era t ion. th e dig i t a l output s are t t l / c m o s or l v d s c o m p a t ibl e an d supp or t e i t h e r t w o s c o m p l e me n t or of f s e t bi n a r y f o r m a t . s e p a r a te output p o w e r s u p p l y p i n s s u p p o r t in t e r f acin g wi th 3.3 v o r 2.5 v cmos log i c. func tio n a l block di agram tra ck- and-hold scalable reference adc 12-bit pipeline core lvds outputs clock mana gement sense vref agnd drgnd drvdd av dd data, overrange in l vds or 2-por t cmos dco? s5 s4 s2 s1 clk+ ds+ vin+ ad9430 12 vin ? ds ? clk? dco+ select cmos or l vds cmos outputs 02607-001 f i gur e 1 . f u nctio n al bl oc k dia g r a m t w o o u t p u t b u s e s s u p p o r t dem u l t i p lexed da t a u p t o 105 ms ps ra t e s in cmos m o de . a da t a sy n c in p u t is s u pp o r t e d fo r p r o p er o u t p ut da t a p o r t a l ig n m e n t in cmos m o de, and a d a t a clo c k output i s a v ai l a bl e f o r prop e r o u tput d a t a t i m i ng . in l v d s m o de, t h e chi p p r o v ide s da t a a t t h e e n c o de clo c k r a te. f a b r ica t ed on an advan c ed bicm os p r o c es s, t h e ad9430 is a v a i la b l e i n a 10 0-le ad , sur f ace - m o u n t pla s t i c p a cka g e (100 e-p a d t q fp) s p ecif ied o v er th e in d u s t r i al t e m p era t ur e ra n g e (C40c t o +85c). product highlights 1. hi g h p e r f o r m a n c e . m a in ta in s 65 db s n r @ 210 m s ps wi t h a 65 mh z in p u t. 2. lo w po w e r . c o n s u m es onl y 1.3 w @ 210 m s ps. 3. ea s e o f u s e . l v ds o u t p u t d a ta a n d o u t p u t c l oc k si gn al allo w i n t e rface to c u r r e n t f p g a te ch nol o g y . t h e on- c h i p re fe re nc e and sa m p le /h o l d p r o v id e f l e x i b ili t y i n sys t em d e si g n . u s e o f a sin g le 3.3 v su p p l y sim p lif i es sys t em p o w e r s u p p l y desig n . 4. ou t o f ra n g e (o r ) . the o r o u t p u t b i t i n dica t e s w h en t h e i n p u t sig n al is b e y o nd t h e s e l e c t e d i n put r a ng e. 5. p i n co m p a t ib le wi th 10 -b i t ad9411 (l vds o n l y ).
ad9430 rev. c | page 2 of 40 table of contents dc specifications ............................................................................. 4 ac specifications .............................................................................. 5 digital specifications ........................................................................ 6 switching specifications .................................................................. 7 absolute maximum ratings ............................................................ 9 explanation of test levels ........................................................... 9 esd caution .................................................................................. 9 pin configurations and function descriptions ......................... 10 ter mi nolo g y .................................................................................... 14 equivalent circuits ......................................................................... 16 typical performance characteristics ........................................... 17 application notes ........................................................................... 24 theory of operation .................................................................. 24 encode input ............................................................................... 24 analog input ............................................................................... 25 ds inputs (ds+, dsC) ................................................................ 25 cmos outputs ........................................................................... 25 lvds outputs ............................................................................. 25 clock outputs (dco+, dcoC) ............................................... 26 volt age reference ....................................................................... 26 noise power ratio testing (npr) ............................................ 26 evaluation board, cmos mode ................................................... 27 power connector ........................................................................ 27 analog inputs ............................................................................. 27 gain .............................................................................................. 27 encode ..................................................................................... 27 volt age reference ....................................................................... 27 data format select ..................................................................... 27 i/p timing select ........................................................................ 27 timing controls ......................................................................... 27 cmos data outputs .................................................................. 27 dac outputs .............................................................................. 28 crystal oscillator ........................................................................ 28 optional amplifier ..................................................................... 28 troubleshooting .......................................................................... 28 evaluation board, lvds mode ...................................................... 34 power connector ........................................................................ 34 analog inputs ............................................................................. 34 gain .............................................................................................. 34 clock ............................................................................................ 34 volt age reference ....................................................................... 34 data format select ..................................................................... 34 data outputs ............................................................................... 34 crystal oscillator ........................................................................ 34 outline dimensions ....................................................................... 40 ordering guide .......................................................................... 40
ad9430 rev. c | page 3 of 40 revision history 11/04rev. b to rev. c changes to specifications ............................................................. 4 changes to figure 60 ................................................................. 31 changes to lvds pcb bom .................................................... 35 changes to figure 68 (evaluation boardlvds mode) ...... 36 updated outline dimensions ................................................... 40 7/03rev. a to rev. b changed order of figure 1 and figure 2 ................................... 5 updated tpc 13 .......................................................................... 14 changes to lvds outputs section....................................... 20 add new ad9430 evaluation board, lvds mode section ...................................................................................... 27 updated outline dimensions ........................................ 32 3/03rev. 0 to rev. a upgraded for ad9430-210 ............................................universal changes to features ............................................................... 1 changes to product highlights .................................... 1 changes to specifications ................................................... 2 changes to figure 2 ...................................................................... 5 changes to ordering guide ................................................ 6 change to pin function descriptions ........................ 7 edits to output propagation delay section. ........................... 10 added tpcs 5C8, 10C12, 14, 16, 18, 20, 22, 27, 31C32, 34 ... 12 changes to tpcs........................................... 17, 19, 26, 35C36, 38 added text to encode input section ................................ 18 added ds inputs section ....................................................... 19 change to table i ....................................................................... 19 changes to lvds outputs section........................................... 20 changes to voltage reference section ...................................... 20 replaced figure 12...................................................................... 20 change to troubleshooting section .......................................... 22 updated outline dimensions.......................................... 27 5/02revision 0: initial version
ad9430 rev. c | page 4 of 40 dc specifications avdd = 3.3 v, drvdd = 3.3 v, t min = C40c, t max = +85c, f in = C0.5 dbfs, internal reference, full scale = 1.536 v, lvds output mode, unless otherwise noted. table 1 . ad9430-170 ad9430-210 parameter temp test level min typ max min typ max unit resolution 12 bits accuracy no missing codes full vi guaranteed guaranteed offset error 25c i C3 +3 C3 +3 mv gain error 25c i C5 +5 C5 +5 % fs differential nonlinearity (dnl) 25c i C1 0.3 +1 C1 0.3 +1 lsb full vi C1 0.3 +1.5 C1 0.3 +1.5 lsb integral nonlinearity (inl) 25c i C1.5 0.5 +1.5 C1.75 0.3 +1.75 lsb full vi C2.25 0.5 +2.25 C2.5 0.3 +2.5 lsb temperature drift offset error full v 58 58 v/c gain error full v 0.02 0.02 %/c reference out (vref) full v +0.12/C0.24 +0.12/C0.24 mv/c reference reference out (vref) 25c i 1.15 1.235 1.3 1.15 1.235 1.3 v output current 1 25c iv 3.0 3.0 ma i vref input current 2 25c i 20 20 ma i sense input current 2 25c i 1.6 5.0 1.6 5.0 ma analog inputs (vin+, vinC) 3 differential input voltage range (s5 = gnd) full v 1.536 1.536 v differential input voltage range (s5 = avdd) full v 0.766 0.766 v input common-mode voltage full vi 2.65 2.8 2.9 2.65 2.8 2.9 v input resistance full vi 2.2 3 3.8 2.2 3 3.8 k? input capacitance 25c v 5 5 pf power supply (lvds mode) avdd full iv 3.1 3.3 3.6 3.2 3.3 3.6 v drvdd full iv 3.0 3.3 3.6 3.0 3.3 3.6 v supply currents: i analog (avdd = 3.3 v) 4 full vi 335 372 390 450 ma i digital (drvdd = 3.3 v) 4 full vi 55 62 55 62 ma power dissipation 4 full vi 1.29 1.43 1.5 1.7 w power supply rejection 25c v C7.5 C7.5 mv/v power supply (cmos mode) avdd full iv 3.1 3.3 3.6 3.2 3.3 3.6 v drvdd full iv 3.0 3.3 3.6 3.0 3.3 3.6 v supply currents: i avdd (avdd = 3.3 v) 5 full iv 335 372 390 450 ma i drvdd (drvdd = 3.3 v) 5 full iv 24 30 30 30 ma power dissipation 5 full iv 1.1 1.3 w power supply rejection 25c v C7.5 C7.5 mv/v 1 internal reference mode; sense = floats. 2 external reference mode; sense = drvdd, vref driven by external 1.23 v reference. 3 s5 (pin 1) = gnd. see analog input section. s5 = gnd in all dc, ac tests unless otherwise specified. 4 i avdd and i drvdd are measured with an analog input of 10.3 mhz, C0.5 dbfs, sine wave, rated encode rate, and in lvds output mode. see typical pe rformance characteristics and applicat ion notes sect ions for i drvdd . power consumption is measured with a dc input at rated encode rate in lvds output mode. 5 i avdd and i drvdd are measured with an analog input of 10.3 mhz, C0.5 dbfs, sine wave, rated encode rate, and in cmos output mode. see typical p erformance characteristics and applicat ion notes sect ions for i drvdd . power consumption is measured with a dc input at rated encode rate in cmos output mode.
ad9430 rev. c | page 5 of 40 ac specifications avdd = 3.3 v, drvdd = 3.3 v, t min = C40c, t max = +85c, f in = C0.5 dbfs, internal reference, full scale = 1.536 v, lvds output mode, unless otherwise noted. table 2 1 . ad9430-170 ad9430-210 parameter temp test level min typ max min typ max unit snr analog input @ C0.5 dbfs 10 mhz 25c i 63.5 65 62.5 64.5 db 70 mhz 25c i 63 65 62.5 64.5 db 100 mhz 25c v 65 64.5 db 240 mhz 25c v 61 61 db sinad analog input @ C0.5 dbfs 10 mhz 25c i 63.5 65 62.5 64.5 db 70 mhz 25c i 63 65 62.5 64.5 db 100 mhz 25c v 65 64.5 db 240 mhz 25c v 60 60 db effective number of bits (enob) 10 mhz 25c i 10.2 10.6 10.2 10.5 bits 70 mhz 25c i 10.2 10.6 10.2 10.5 bits 100 mhz 25c v 10.6 10.5 bits 240 mhz 25c v 9.8 9.8 bits worst harmonic (2nd or 3rd) analog input @ C0.5 dbfs 10 mhz 10 mhz 25c i C85 C75 C84 C74 dbc 70 mhz 25c i C85 C75 C84 C74 dbc 100 mhz 25c v C77 C77 dbc 240 mhz 25c v C63 C63 dbc worst harmonic (4 th or higher) analog input @ C0.5 dbfs 10 mhz 10 mhz 25c i C87 C78 C87 C77 dbc 70 mhz 25c i C87 C78 C87 C77 dbc 100 mhz 25c v C77 C77 dbc 240 mhz 25c v C63 C63 dbc two-tone imd 2 f1, f2 @ C7 dbfs 25c v C75 C75 dbc analog input bandwidth 25c v 700 700 mhz 1 all ac specifications tested by driving clk+ and clkC differentially. 2 f1 = 28.3 mhz, f2 = 29.3 mhz.
ad9430 rev. c | page 6 of 40 digital specifications avdd = 3.3 v, drvdd = 3.3 v, t min = C40c, t max = +85c, unless otherwise noted. table 3. test ad9430-170 ad9430-210 parameter temp level min typ max min typ max unit encode and ds inputs (clk+, clkC, ds+, dsC) 1 differential input voltage 2 full iv 0.2 0.2 v common-mode voltage 3 full vi 1.375 1.5 1.575 1.375 1.5 1.575 v input resistance full vi 3.2 5.5 6.5 3.2 5.5 6.5 k? input capacitance 25c v 4 4 pf logic inputs (s1, s2, s4, s5) logic 1 voltage full iv 2.0 2.0 v logic 0 voltage full iv 0.8 0.8 v logic 1 input current full vi 190 190 a logic 0 input current full vi 10 10 a input resistance 25c v 30 30 k? input capacitance 25c v 4 4 pf logic outputs (cmos mode) logic 1 voltage 4 full iv drvdd drvdd v C0.05 C0.05 logic 0 voltage 4 full iv 0.05 0.05 v logic outputs (lvds mode) 4 , 5 v od differential output voltage full vi 247 454 247 454 mv v os output offset voltage full vi 1.125 1.375 1.125 1.375 v output coding twos complement or binary twos complement or binary 1 encode and ds inputs identical on-chip. see equivalent circuits section. 2 all ac specifications tested by driving clk+ and clkC differentially, |(clk+) C (clkC)| > 200 mv. 3 encode inputs common mode can be externally set, such that 0.9 v < enc < 2.6 v. 4 digital output logic levels: drvdd = 3.3 v, c load = 5 pf. 5 lvds r term = 100 ? , lvds output current set resistor (r set ) = 3.74 k ? (1% tolerance).
ad9430 rev. c | page 7 of 40 switching specifications avdd = 3.3 v, drvdd = 3.3 v, t min = C40c, t max = +85c, unless otherwise noted.) table 4. test ad9430-170 ad9430-210 parameter (conditions) temp level min typ max min typ max unit maximum conversion rate 1 full vi 170 210 msps minimum conversion rate 1 full v 40 40 msps clk+ pulse width high (t eh ) 1 full iv 2 12.5 2 12.5 ns clk+ pulse width low (t el ) 1 full iv 2 12.5 2 12.5 ns ds input setup time (t sds ) 2 full iv C0.5 C0.5 ns ds input hold time (t hds ) 2 full iv 1.75 1.75 ns output (cmos mode) valid time (t v ) full iv 2 2 ns propagation delay (t pd ) full iv 3.8 5 3.8 5 ns rise time (tr) (20% to 80%) 25c v 1 1 ns fall time (tf) (20% to 80%) 25c v 1 1 ns dco propagation delay (tcpd) full iv 3.8 5 3.8 5 ns data to dco skew (t pd C t cpd ) full iv C0.5 0 +0.5 C0.5 0 +0.5 ns interleaved mode (a, b latency) fu ll iv 14, 14 14, 14 cycles parallel mode (a, b latency) full iv 15, 14 15, 14 cycles output (lvds mode) valid time (t v ) full vi 2.0 2.0 ns propagation delay (t pd ) full vi 3.2 4.3 3.2 4.3 ns rise time (t r ) (20% to 80%) 25c v 0.5 0.5 ns fall time (t f ) (20% to 80%) 25c v 0.5 0.5 ns dco propagation delay (t cpd ) full vi 1.8 2.7 3.8 1.8 2.7 3.8 ns data to dco skew (t pd C t cpd ) full iv 0.2 0.5 0.8 0.2 0.5 0.8 ns latency full iv 14 14 cycles aperture delay (t a ) 25c v 1.2 1.2 ns aperture uncertainty (jitter, t j ) 25c v 0.25 0.25 ps rms out of range recovery time (cmos and lvds) 25c v 1 1 cycles 1 all ac specifications tested by driving clk+ and clkC differentially. 2 ds inputs used in cmos mode only.
ad9430 r e v. c | pa ge 8 o f 4 0 por t a d a11?d a0 por t b db11?db0 p arallel d a t a out por t a d a11 ?d a0 por t b db11?db0 clk+ clk ? ds+ ds ? interlea ved d a t a out st a tic st a tic st a tic st a tic st a tic inv alid inv alid inv alid inv alid inv alid inv alid inv alid t sds 14 cycles t pd t v n n+2 n+3 n+1 n n+2 n+1 n+3 t cpd t hds dco+ dco? 02607-002 f i g u re 2. c m os ti ming d i ag r a m n? 14 n? 13 n n+1 a in clk+ clk? data out dco+ dco? n n+1 n ? 1 t eh t el 1/f s t pd 14 cycles t cpd 02607-003 f i gure 3. l v ds tim i ng d i agr a m
ad9430 r e v. c | pa ge 9 o f 4 0 absolute maximum ra tings table 5. parameter rating avdd, dr vdd 4 v analog inputs C0.5 v to av dd + 0.5 v digital inputs C0.5 v to dr vd d + 0.5 v refin inputs C0.5 v to av dd + 0.5 v digital output c u rrent 20 ma operating tem p erature C55oc to +125c storage temperature C65oc to +150c maximum junction temperature 150c maximum case temperature 150c ja 1 25c/w, 32c/w 1 typical ja = 32 c/ w (h ea t slug n o t so lde red ) ; t y pi ca l ja = 25 c/w (h ea t s l u g sol d er ed ) for m u lt i l a y er boa r d i n st i l l a i r wi t h so li d g r oun d pla n e. s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h os e list e d i n t h e op era t io nal s e c t ion s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . expl ana t ion of test levels te s t l e v e l i. 100% p r o d uc t i o n t e st ed . ii. 100% p r o d uc t i o n t e st ed a t 25c a nd s a m p le t e s t ed a t sp e c if ie d t e m p e r a t ur es. iii. s a m p l e te ste d on ly . iv. p a r a me te r i s g u ar an te e d b y d e s i g n an d ch ar a c te r i z a t i on te st i n g . v. p a ra m e t e r is a typ i cal val u e o n ly . vi. 100% p r o d uc t i o n t e st ed a t 25c; gua r a n t e ed b y desig n and ch ar a c te r i z a t i on te st i n g for i n d u st r i a l te m p e r a t u r e r a nge ; 100% p r o d uc t i o n t e st ed a t t e m p era t ur e extr em es f o r mi li t a r y de vi ces . esd c a ution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge with out detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad9430 rev. c | page 10 of 40 pin conf igura t ions and f u ncti on descriptions 26 27 28 29 30 55 54 53 52 51 cm o s p i no ut t o p v i ew ( n o t t o s cal e) ad9430 agnd av dd av dd av dd agnd 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 25 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 31 37 agnd ds + ds? av dd agnd clk+ clk? agnd av dd av dd agnd dnc dnc db0 db1 db2 drv dd drgnd db3 db4 80 da9 79 da8 78 da7 77 da6 76 da5 75 drvdd 74 drgnd 73 da4 72 da3 71 da2 70 da1 69 da0 68 dnc 67 drgnd 66 dnc 65 dnc 64 dco+ 63 dco? 62 drvdd 61 drgnd 60 or_b 59 db11 58 db10 57 db9 56 db8 db7 drvdd drgnd db6 db5 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 agnd av dd av dd agnd agnd av dd av dd agnd agnd agnd av dd av dd av dd agnd agnd or_a da1 1 drv dd drgnd da1 0 s5 dnc s4 agnd s2 s1 dnc avdd agnd sense vref agnd agnd avdd avdd agnd agnd avdd avdd agnd vin+ vin? agnd avdd agnd 02607-004 f i g u re 4. c m os d u al-m ode pin o ut
ad9430 rev. c | page 11 of 40 table 6. pin function descriptions (cmos mode) pin number mnemonic function 1 s5 full-scale adjust pin. avdd sets f s = 0.768 v p-p differential, gnd sets f s = 1.536 v p-p differential. 2, 7, 42, 43, 65, 66, 68 dnc do not connect. 3 s4 interleaved, parallel select pin. high = interleaved. 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100 agnd 1 analog ground. 5 s2 output mode select. low = dual-port cmos, high = lvds. 6 s1 data format select. low = binary, high = twos complement for both cmos and lvds mode. 8, 14, 15, 18, 19, 24, 27, 28, 29, 34, 39, 40, 88, 89, 90, 94, 95, 98, 99 avdd 3.3 v analog supply. 10 sense reference mode select pin. float for internal reference operation. 11 vref 1.235 v reference i/ofunction dependent on sense. 21 vin+ analog inputtrue. 22 vinC analog inputcomplement. 32 ds+ data sync (input)true. tie low if not used. 33 dsC data sync (input)comp lement. tie high if not used. 36 clk+ clock inputtrue. 37 clkC clock inputcomplement. 44 db0 b port output data bit (lsb). 45 db1 b port output data bit. 46 db2 b port output data bit. 47, 54, 62, 75, 83 drvdd 3.3 v digital output supply (3.0 v to 3.6 v). 48, 53, 61, 67, 74, 82 drgnd 1 digital output ground. 49 db3 b port output data bit. 50 db4 b port output data bit. 51 db5 b port output data bit. 52 db6 b port output data bit. 55 db7 b port output data bit. 56 db8 b port output data bit. 57 db9 b port output data bit. 58 db10 b port output data bit. 59 db11 b port output data bit (msb). 60 or_b b port overrange. 63 dcoC data clock outputcomplement. 64 dco+ data clock outputtrue. 69 da0 a port output data bit (lsb). 70 da1 a port output data bit. 71 da2 a port output data bit. 72 da3 a port output data bit. 73 da4 a port output data bit. 76 da5 a port output data bit. 77 da6 a port output data bit. 78 da7 a port output data bit. 79 da8 a port output data bit. 80 da9 a port output data bit. 81 da10 a port output data bit. 84 da11 a port output data bit (msb). 85 or_a a port overrange. 1 agnd and drgnd should be tied to gether to a common ground plane.
ad9430 rev. c | page 12 of 40 26 27 28 29 30 55 54 53 52 51 lvds pinout top view (not to scale) ad9430 agnd av dd av dd av dd agnd 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 25 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 31 37 agnd gnd av dd av dd agnd clk+ clk ? agnd av dd av dd agnd dnc dnc dnc dnc dnc drv dd drgnd d0 ? d0 + 80 d1 1? 79 d 10+ 78 d1 0? 77 d9 + 76 d9 ? 75 drvdd 74 drgnd 73 d8+ 72 d8? 71 d7+ 70 d7? 69 d6+ 68 d6? 67 drgnd 66 d5+ 65 d5? 64 dco+ 63 dco? 62 drvdd 61 drgnd 60 d4+ 59 d4? 58 d3+ 57 d3? 56 d2+ d2? drvdd drgnd d1+ d1? 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 agnd av dd av dd agnd agnd av dd av dd agnd agnd agnd av dd av dd av dd agnd agnd or+ or? drv dd drgnd d 11+ s5 dnc s4 agnd s2 s1 lvdsbias avdd agnd sense vref agnd agnd avdd avdd agnd agnd avdd avdd agnd vin+ vin? agnd avdd agnd 02607-005 f i gure 5. l v ds mod e p i nout
ad9430 rev. c | page 13 of 40 table 7. pin function descriptions (lvds mode) pin number mnemonic function 1 s5 full-scale adjust pin. avdd sets f s = 0.768 v p-p differential, gnd sets f s = 1.536 v p-p differential. 2, 42 to 46 dnc do not connect. 3 s4 control pin for cmos mode. tie low when operating in lvds mode. 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100 agnd 1 analog ground. 5 s2 output mode select. gnd = dual-port cmos; avdd = lvds. 6 s1 data format select. gnd = binary, avdd = twos complement. 7 lvdsbias set pin for lvds output current. place 3.74 kw resistor terminated to ground. 8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34, 39, 40, 88, 89, 90, 94, 95, avdd 3.3 v analog supply. 98, 99 10 sense reference mode select pin. float fo r internal reference operation. 11 vref 1.235 v reference i/ofunction dependent on sense. 21 vin+ analog inputtrue. 22 vinC analog inputcomplement. 32 gnd data sync (input)not us ed in lvds mode. tie to gnd. 36 clk+ clock inputtrue (lvpecl levels). 37 clkC clock inputcomplement (lvpecl levels). 47, 54, 62, 75, 83 drvdd 3.3 v digital output supply (3.0 v to 3.6 v). 48, 53, 61, 67, 74, 82 drgnd 1 digital output ground. 49 d0C d0 complement output bit (lsb). 50 d0+ d0 true output bit (lsb). 51 d1C d1 complement output bit. 52 d1+ d1 true output bit. 55 d2C d2 complement output bit. 56 d2+ d2 true output bit. 57 d3C d3 complement output bit. 58 d3+ d3 true output bit. 59 d4C d4 complement output bit. 60 d4+ d4 true output bit. 63 dcoC data clock outputcomplement. 64 dco+ data clock outputtrue. 65 d5C d5 complement output bit. 66 d5+ d5 true output bit. 68 d6C d6 complement output bit. 69 d6+ d6 true output bit. 70 d7C d7 complement output bit. 71 d7+ d7 true output bit. 72 d8C d8 complement output bit. 73 d8+ d8 true output bit. 76 d9C d9 complement output bit. 77 d9+ d9 true output bit. 78 d10C d10 complement output bit. 79 d10+ d10 true output bit. 80 d11C d11 complement output bit. 81 d11+ d11 true output bit. 84 orC overrange complement output bit. 85 or+ overrange true output bit. 1 agnd and drgnd should be tied to gether to a common ground plane.
ad9430 rev. c | page 14 of 40 terminology ana l og b a n d w i d t h t h e a n al og in p u t f r eq ue n c y a t wh i c h t h e s p ect r al po w e r o f th e f u ndam e n t a l f r e q uen c y (as det e r m ine d b y t h e f f t a n a l y s is) is r e d u ced b y 3 db . ap e r t u r e d e l a y the de l a y b e t w e e n t h e 50 % p o i n t o f t h e r i sin g e d g e o f t h e en c o de co m m a nd an d t h e i n st an t a t w h ich t h e ana l og in p u t is s a m p le d . ap e r t u r e un c e r t a i n t y ( j i t t e r ) the s a m p le -t o-s a m p le va r i a t io n in a p er t u r e dela y . cr o s s t al k c o u p lin g o n t o o n e c h a n ne l be in g dr i v e n b y a l o w le ve l (C40 dbfs) sig n a l w h en t h e a d j a cen t in t e r f er in g cha nne l is dr i v en b y a f u l l - s ca le sig n a l . d i ff e r e n t i al a n alo g i n p u t r e s i s t a n c e , d i ff e r e n t i al a n alo g input c a p a c i t a n c e , a n d d i f f erent i a l a n a l o g input imp e d a n c e the r e a l and co m p lex im p e dances m e a s ur e d a t e a ch a n a l o g in p u t p o r t . t h e re s i st anc e is me asu r e d st a t i c a l ly and t h e ca p a ci t a n c e and dif f er en t i al i n pu t im p e dan c es ar e m e as ur e d wi t h a n e tw o r k a n a l y z er . d i f f erent i a l a n a l o g input v o lt a g e r a ng e the p e ak- t o-p e ak dif f er en t i a l vol t a g e t h a t m u st b e a p plie d t o t h e co n v er t e r t o g e n e ra t e a f u l l - s cale r e sp o n s e . p e ak dif f er en t i a l v o l t a g e is co m p u t e d b y obs e r v i n g t h e v o l t a g e o n a si n g le p i n a nd sub t rac t in g t h e v o l t a g e f r o m t h e o t h e r p i n, w h ich is 180 o u t o f p h as e . p e a k -t o-p e a k dif f er en tial is com p u t e d b y r o ta tin g the in p u t s p h as e 180 a nd a g ain t aking th e p e a k m e as ur e m en t. the dif f er en ce i s t h e n co m p u t e d b e t w e e n b o t h peak m e a s u r em e n t s . d i f f erenti a l n o n l i n e a r i ty t h e devia t i o n o f a n y cod e wi d t h f r o m a n i d eal 1 l s b s t ep . ef f e c t ive n u mb er o f b i ts (eno b) c a lc u l a t e d f r o m t h e m e as ur ed s n r bas e d on t h e e q u a tio n 02 . 6 76 . 1 db snr enob measured ? = en c o d e pu ls e w i d t h/d u ty cy cl e pu ls e wid t h hig h is t h e minim u m am o u n t o f tim e t h e en c o de p u ls e (c lo c k p u ls e) sh o u ld be lef t in l o g i c 1 s t a t e t o ac hie v e ra te d p e r f o r ma n c e; p u ls e wi d t h lo w is t h e min i m u m t i me t h e en c o d e p u ls e s h o u l d b e lef t in lo w sta t e . s e e timin g im pli c a t io n s o f cha n g i n g t eh i n t h e a p plic a t io n n o t e s, e n co de i n p u t s e c t io n. a t a g i v e n clo c k r a t e , t h e s e sp e c if ica t io n s def i n e an a c c e pt abl e e n c o de d u t y c y cl e. f u l l - s c a l e input p o wer e x p r ess e d in dbm. c o m p ute d u s in g t h e fol l o w i n g e q u a t i on: ? ? ? ? ? ? ? ? ? ? ? ? = 001 . 0 log 10 2 input rms fullscale fullscale z v power ga in e r r o r the dif f er en ce b e tw e e n t h e m e as ur e d an d ide a l f u l l -s cale in put v o l t a g e ra n g e o f t h e ad c. ha r m on i c d i s t or t i on , s e c o n d the ra t i o o f t h e r m s sig n al a m pl i t u d e t o t h e r m s val u e o f t h e s e c o n d h a rm o n i c c o m p o n e n t , r e p o rt e d i n d b c . ha r m on i c d i s t or t i on , t h i r d the ra t i o o f t h e r m s sig n al a m pl i t u d e t o t h e r m s val u e o f t h e t h ir d ha r m o n ic co m p on e n t, r e p o r t e d in db c. inte g r a l n o n l i n e a r i t y the de v i a t ion o f t h e t r a n sfer f u n c t i on f r o m a r e fer e n c e line m e as ur ed in f r ac tio n s o f 1 ls b usin g a b est s t r a ig h t lin e det e r m i n e d b y a le ast s q ua r e c u r v e f i t. minim u m c o n v ersi o n r a t e the enc o de ra t e a t which t h e s n r of t h e l o w e s t a n alog sig n a l f r e q u e nc y d r op s b y no m o re t h an 3 d b b e l o w t h e g u ar an te e d l i m i t . ma x i mu m c o nve r si on r a te the enc o de ra t e a t w h ich p a r a m e t r ic t e st i n g i s p e r f o r m e d . ou t p u t p r o p aga t io n de la y th e de la y b e tw e e n a dif f er en tia l cr os sin g o f clk+ a n d clkC a n d t h e t i m e w h en a l l o u t p u t da t a b i ts a r e w i t h in val i d log i c le v e l s. n o is e (f o r an y r a n g e w i thin t h e ad c) cal c ula t e d a s f o ll o w s : ? ? ? ? ? ? ? ? = 10 10 001 . 0 dbfs dbc dbm noise signal snr fs z v w h er e z is t h e i n p u t im p e dan c e , fs is t h e f u l l s c ale o f t h e de vic e fo r t h e f r e q uen c y in q u es t i on, snr is t h e va l u e o f t h e p a r t ic u l a r in p u t le vel, and sig n al is t h e sig n al le ve l wi thin th e ad c, r e p o r t ed in db b e lo w f u l l s c ale . this val u e in c l udes in p u t leve l s b o th th e r m a l a n d q u a n ti z a t i o n n o i s e . p o wer s u pply rej e c t i o n r a ti o the ra t i o o f a cha n g e i n i n p u t o f fs et v o l t a g e t o a cha n g e i n p o we r su p p ly v o l t age.
ad9430 rev. c | page 15 of 40 signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set 1 db below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious component may or may not be a harmonic. may be reported in dbc (i.e., degrades as signal level is lowered) or dbfs (always related back to converter full scale). two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product ; reported in dbc. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. may be reported in dbc (i.e., degrades as signal level is lowered) or in dbfs (always related back to converter full scale). worst other spur the ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dbc. transient resp onse time the time it takes for the adc to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. out-of-range recovery time the time it takes for the adc to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale.
ad9430 rev. c | page 16 of 40 equiv a lent ci rcuits clk+ or ds+ 12k ? 10k ? 150 ? 150 ? 12k ? 10k ? av d d clk ? or ds? 02607-006 f i gure 6. enc o de and ds inputs vin+ 3.5k ? 20k ? 3.5k ? 20k ? av d d vin ? 02607-007 fi g u r e 7 . a n a l o g i n p u t s s1 , s2 , s4, s 5 vd d 30k ? 02607-008 fi g u r e 8 . s 1 - s 5 i n p u t s a1 vref 1k ? sense 200 ? 0.1 f disable a1 vd d k full scale s5 = 0 ? > k = 1.24 s5 = 1 ? > k = 0.62 ? + 1v 02607-009 f i gur e 9 . vref , sense i/ o dx dr v dd 02607-010 f i gure 1 0 . d a ta o u tputs ( c mos mo de) dr vdd dx? dx+ v v v v 02607-011 f i gure 1 1 . d a ta o u tputs (l vds mo de)
ad9430 rev. c | page 17 of 40 8 5 typical perf orm ance cha r acte ristics cha r ts a t 170 m s ps, 210 ms ps f o r C170, C210 grades, r e s p ec ti ve l y . a v d d , dr vd d = 3.3 v , t = 25c, a in dif f er en t i al dr i v e , f u l l s c ale = 1.536 v , in t e r n al r e f e r e n c e u n les s o t h e r w is e n o t e d . mhz 04 0 10 20 30 50 60 70 80 db 0 ?100 ?1 0 ?2 0 ?8 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?9 0 snr = 65.2db sinad = 65.1db h2 = ? 88.8dbc h3 = ? 88.1dbc sfdr = 87dbc 02607-012 f i g u re 12. fft : f s = 17 0 m s ps, a in = 10. 3 m h z @ ?0. 5 dbf s , l v ds m o de mhz 04 0 10 20 30 50 60 70 80 db 0 ?100 ?10 ?20 ?80 ?30 ?40 ?50 ?60 ?70 ?90 8 5 snr = 65.1db sinad = 64.9db fund = ? 0.50dbfs h2 = ? 88.6dbc h3 = ? 94.6dbc sfdr = 85.9dbc 02607-013 f i g u re 13. fft : f s = 17 0 m s ps, a in = 65 mh z @ C0.5 dbfs, l v ds mode mhz 04 0 10 20 30 50 60 70 80 db 0 ?100 ?1 0 ?2 0 ?8 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?9 0 8 5 snr = 64.93db sinad = 64.85db fund = ? 0.44dbfs h2 = ? 92.1dbc h3 = ? 90.1dbc sfdr = 75.6dbc 02607-015 f i g u re 14. fft : f s = 17 0 m s ps, a in = 65 mh z @ C0.5 dbfs, c m os mode mhz 04 0 10 20 30 50 60 70 80 db 0 ?100 ?1 0 ?2 0 ?8 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?9 0 8 5 snr = 62.99dbfs sinad = 61.45dbfs h2 = ? 66.8dbc h3 = ? 82.5dbc sfdr = 66.1dbc 02607-015 f i g u re 15. fft : f s = 17 0 m s ps, a in = 10. 3, m h z @ C 0 .5 dbfs , sing le -e nd ed input, f u ll s c al e = 0 . 76 v , l v ds m o de db 0 ?1 0 ?2 0 ?3 0 ?4 0 ?5 0 ?6 0 ?7 0 ?8 0 ?9 0 ?100 0 1 53 0 4 5 6 0 7 59 0 1 0 5 snr = 63.6db sinad = 62.9db h2 = ? 82.5dbc h3 = ? 78.6dbc sfdr = 77.7dbc mhz 02607-016 f i g u re 16. fft : f s = 21 0 m s ps, a in = 10. 3 m h z @ C 0 . 5 dbfs , l v ds m o de db 0 ?20 ?10 ?30 ?40 ?60 ?70 ?50 ?80 ?90 ? 100 0 1 5 3 0 4 5 6 0 7 5 9 0 105 snr = 63.1db sinad = 62.8db h2 = ? 81.1dbc h3 = ? 76dbc sfdr = ? 76dbc mhz 02607-017 f i g u re 17. fft : f s = 21 0 m s ps, a in = 65 mh z @ C 0 .5 dbfs, c m os mode
ad9430 rev. c | page 18 of 40 db 0 ?1 0 ?2 0 ?3 0 ?4 0 ?6 0 ?7 0 ?8 0 ?9 0 ?5 0 ?100 0 1 5 3 0 4 5 6 0 7 5 9 0 105 mhz snr = 63.5db sinad = 62.6db h2 = ? 79dbc h3 = ? 76.1dbc sfdr = 75.2dbc 02607-018 f i g u re 18. fft : f s = 21 0 m s ps, a in = 65 mh z @ C0.5 dbfs, l v ds mode a in (mhz) db 85 80 75 70 65 60 55 50 45 40 0 100 150 250 350 50 200 300 400 sfdr snr sinad full scale = 1.5 02607-019 f i gure 19. snr, si n a d , and sfdr vs. a in fre q u e n c y , f s = 21 0 m s ps, a in @ C0 .5 d b f s , l v d s mo de a in (mhz) 0 200 400 50 100 150 250 300 350 db 100 40 90 50 80 70 60 second third sfdr 02607-020 f i gur e 2 0 . ha rm onic di stor ti on (s e c ond a n d thir d) and sfdr v s . a in fr e q u e n c y 0 1 53 0 4 56 07 59 0 1 0 5 db 0 ?6 0 ?9 0 ?4 0 ?2 0 ?7 0 ?3 0 ?1 0 ?5 0 mhz ?8 0 ?100 snr = 63.3db sinad = 63.1db h2 = ? 80.38dbc h3 = ? 81.8dbc sfdr = 80.8dbc 02607-021 f i g u re 21. fft : f s = 21 3 m s p , a in = 10 0 mhz @ C0 .5 dbfs, l v ds mo de a in (mhz) db 85 80 75 70 65 60 55 50 45 40 0 100 150 250 350 50 200 300 400 sinad snr full scale = 0.75 02607-022 f i gure 22. snr, and sinad vs. a in fr e q u e n c y ; f s = 21 0 m s ps , a in @ C0 .5 d b f s , l v d s mo de , f u ll sc a l e = 0 . 76 v a in (mhz) 0 200 400 50 100 150 250 300 350 db 100 40 90 50 80 70 60 second third sfdr 02607-023 f i gur e 2 3 . ha rm onic di stor ti on (s e c ond a n d thir d) a n d sfdr vs. a in fre q u e n c y , f s = 170 ms p s , c m os mo de
ad9430 rev. c | page 19 of 40 a in (mhz) db 70 66 68 60 62 64 58 56 54 52 50 0 100 150 50 200 250 300 350 400 ?170 sinad ?210 sinad ? 210 snr ?170 snr 02607-024 f i gure 24. snr, and sinad vs. a in fr e q u e n c y ; f s = 17 0, 2 1 0 m s ps, a in @ C0 .5 d b f s , l v d s mo de a in (mhz) db 85 80 75 70 65 60 55 50 45 40 0 100 150 250 350 50 200 300 400 sinad snr sfdr 02607-025 f i gure 25. snr, and sinad , sfdr vs. a in fre q u e n c y ; f s = 21 0 m s ps, a in @ C0.5 dbfs, c m os mode mhz 04 0 10 20 30 50 60 70 80 db 0 ?100 ?10 ?20 ?80 ?30 ?40 ?50 ?60 ?70 ?90 8 5 sfdr = 75dbc 02607-026 f i g u re 26. t w o - t o n e int e r m odu l at io n d i s t o r t i on (28. 3 m h z and 29 .3 m h z; l v ds m o d e , f s = 17 0 m s ps) db 0 ?30 ?60 ?90 ? 120 0 1 02 03 04 0 5 06 0 8 09 0 1 0 0 70 mhz sfdr = 63dbc 02607-027 f i g u re 27. t w o - t o n e int e r m odu l at io n d i s t o r t i on ( 5 9 m h z and 60 m h z), lv d s m o d e , f s = 210 msp s mhz 0 250 50 100 150 200 db 95 50 90 55 80 75 65 85 70 60 sinad sfdr 02607-028 f i gure 28. sinad and sfdr vs. clock rate (a in = 10. 3 m h z @ C0. 5 dbf s , l v ds m o de), C 1 7 0 gr ade mhz db 85 80 75 70 65 60 55 50 45 40 0 100 150 250 50 200 sinad snr sfdr 02607-029 f i gure 29. snr, and sinad , sfdr vs. clock rate (a in = 1 0 . 3 mh z, @ C0. 5 dbf s ), l v ds m o de , C 2 10 gr ade
ad9430 rev. c | page 20 of 40 analog suppl y current cmos mode analog suppl y current l vds mode output suppl y current l vds mode output suppl y current cmos mode encode (msps) 100 220 140 160 180 200 120 i av dd (analog s u p p l y curre nt) (ma) 400 0 350 50 250 150 300 200 100 i drv dd (outp u t s u p p l y curre nt) (ma) 80 60 40 20 0 02607-030 f i g u re 30. i av d d and i dr vdd vs . clo c k ra te ( a in = 10.3 mh z @ C0.5 dbfs) 17 0 m s ps g r ad e , c lo a d = 5pf encode (msps) i av dd (analog s u p p l y curre nt) (ma) i drv dd (outp u t s u p p l y curre nt) (ma) 450 400 350 300 250 200 150 100 50 0 90 80 70 60 50 40 30 20 10 0 100 140 160 200 220 240 120 180 analog supply current lvds mode output supply current lvds mode output supply current cmos mode analog supply current cmos mode 02607-031 f i g u re 31. i av d d and i dr vdd vs . clo c k ra te (a in = 10. 3 m h z @ C0. 5 dbf s ) 2 1 0 m s ps gr ad e , c lo a d = 5 pf sinad snr sfdr encode positive duty cycle (%) 10 60 90 20 40 50 70 80 30 db 85 50 80 75 70 65 60 55 02607-032 f i gure 32. sinad and sfdr vs. clock p u lse w i dth high (a in = 10. 3 m h z @ C0. 5 dbf s , 17 0 m s p s , l v ds) encode positive duty cycle (%) db 80 75 70 65 60 55 50 20 40 50 70 30 60 80 sinad snr sfdr 02607-033 f i gure 33. snr, si n a d , and sfdr vs. e n c o de p u lse w i dt h high, (a in = 10. 3 mh z @ C0.5 dbfs, 210 ms ps , l v ds) i load (ma) 08 147 2 v re fout (v ) 1.4 0 1.2 1.0 0.8 0.6 0.4 0.2 r o = 13 ? typ 02607-034 5 36 f i g u re 34. v ref o u t vs . i lo a d tempera ture (c) ?50 1 0 9 5 ? 3 0 ? 10 30 50 70 90 gain err o r ( % ) ?2.0 1.5 ?1.0 1.0 0.5 0 ? 0.5 ? 1.5 % gain err or using ext ref 2.0 02607-035 f i g u re 35. f u ll- s c al e g a in e r r o r v s . t e mpe r at u r e (a in = 1 0 . 3 m h z @ C 0 .5 dbfs, 17 0 m s ps /2 10 m s ps, l v ds)
ad9430 rev. c | page 21 of 40 av dd (v) 2.5 3.1 2.7 2.9 3.3 3.5 3.7 3.9 v re f (v ) 1.250 1.225 1.230 1.245 1.240 1.235 02607-036 f i g u re 36. v ref o u t p ut v o ltag e vs. a v dd tempera ture (c) ?50 1 0 ?30 ? 10 30 50 70 90 db 95 60 90 70 85 80 75 65 third second sfdr snr sinad 02607-037 f i gure 37. snr, si n a d , sfdr vs. t e mper atu r e (a in = 1 0 . 3 mh z @ C 0 .5 dbfs, 17 0 ms ps ) temperature (c) db 65 64 63 62 61 60 59 58 57 56 55 ?45 ? 5 1 5 5 5 ?25 3 5 7 5 avdd = 3.6 avdd = 3.3 av dd = 3 . 135 avdd = 3.0 02607-038 f i gure 38. sinad vs. t e mp e r atu r e , a v dd (a in = 7 0 m h z @ C 0 . 5 db , 2 10 m s ps, l v ds mod e ) code 0 4000 500 1500 2500 3000 1000 2000 3500 lsb 1.00 ? 1.00 0.75 ? 0.75 0.25 ? 0.25 0.50 0 ? 0.50 02607-039 f i g u re 39. t y pic a l i n l pl ot (a in = 10.3 mh z @ C0.5 dbfs, 170 m s ps, l v ds) code 0 4000 500 1500 2500 3000 1000 2000 3500 lsb 1.00 ?1.00 0.75 ?0.75 0.25 ?0.25 0.50 0 ?0.50 02607-040 f i g u re 40. t y pic a l d n l pl ot (a in = 10.3 mh z @ C0.5 dbfs) analog input level (dbfs) ? 100 0 ?70 ? 50 ?30 ? 20 ?60 ? 40 ?10 ?8 0 ?90 db 100 0 70 10 50 30 60 40 20 80 90 sfdr ?dbfs sfdr ? dbc 80db reference line 02607-041 f i g u re 41. sfdr v s . a in input l e ve l , a in @ 10 .3 m h z , 17 0 msp s , l v ds m o de
ad9430 rev. c | page 22 of 40 db 90 80 70 60 50 40 30 20 10 0 ?90 ? 70 ?60 ? 40 ?20 ?80 ? 50 ?30 ? 10 0 sfdr dbc lvds mode full scale = 1.5 sfdr dbc cmos mode full scale = 1.5 80db reference line 02607-042 f i g u re 42. sfdr v s . a in input l e ve l , a in @ 10 .3 m h z, 2 1 0 m s ps, lv d s / c m o s m o d e s db 90 80 70 60 50 40 30 20 10 0 ?90 ? 70 ?60 ? 40 ?20 ?80 ? 50 ?30 ? 10 0 sfdr dbc lvds mode full scale = 1.5 sfdr dbc lvds mode full scale = 0.75 80db reference line 02607-043 f i g u re 43. sfdr v s . a in input l e ve l , a in @ 1 0 . 3 mhz , 2 1 0 ms p s , l v d s mo d e , f u l l s c ale = 0. 76 v / 1.5 3 6 v mhz 2.65 42.5 21.25 n o ise in pu t level ( d b ) 0 ?140 ?40 ?120 ?100 ?60 ?80 ?20 npr = 56.95db encode = 170msps no tch @ 19mhz 02607-044 f i g u re 44. no is e p o wer r a t i o plot mhz db 0 ?2 0 ?4 0 ?6 0 ?8 0 ?100 19.2 38.4 19.2 47.6 02607-045 f i gure 45. w - cdm a f o ur chan ne ls ce ntered at 3 8 . 4 mh z , f s = 1 5 3 .6 mh z , l v d s mode full-scale range (v) 0 2.5 2.0 1.0 1.5 0.5 db 90 0 70 10 50 30 60 40 20 80 sinad snr sfdr 02607-046 f i gure 46. snr, and sinad . sfdr v s . f u ll-s c a l e ra ng e , s5 = 0, f u l l -s c a le rang e v a r i ed by adjus t ing v r e f , 170 m s ps temperature ( c) ? 4 0 100 60 20 40 ?20 0 80 ns 4.5 2.5 4.0 3.5 3.0 tpd tcpd 02607-047 f i g u re 47. p r opag a t ion d e l a y v s . t e mper at u r e , l v d s m o d e , 17 0 m s ps/ 2 10 m s p s
ad9430 rev. c | page 23 of 40 tcpd (clock out rising) tempera ture ( c) ? 4 0 100 60 20 40 ?2 0 0 8 0 ns 4.5 2.5 4.0 3.5 3.0 tpdf (d a t a f alling) tpdr (d a t a rising) 02607-048 f i g u re 48. p r opag a t ion d e l a y v s . t e mper at u r e , c m os mo d e , 1 7 0 msp s /2 10 ms p s rset (k ? ) 01 4 10 6 21 2 v dif (mv ) 900 0 700 500 300 800 600 400 200 100 1.4 0.5 1.2 1.0 0.8 1.3 1.1 0.9 0.7 0.6 v os (v ) v os v od 02607-049 8 4 f i gure 49. l v ds o u tput s w ing , com m o n-mod e v o ltag e v s . rse t , p l aced at l v dsbia s , 1 70 m s ps /2 1 0 m s ps
ad9430 rev. c | page 24 of 40 appli c a t ion notes theor y of oper a t ion the ad9430 a r c h i t ec t u r e is o p t i mize d f o r hig h s p eed and eas e o f us e . the a n al og in p u ts dr i v e a n in t e g r a t e d hig h ban d wid t h tra c k - a n d - h o ld ci r c ui t tha t sa m p le s th e si gnal p r i o r t o q u a n tiz a ti o n b y th e 12- b i t co r e . f o r ea se o f use , th e pa r t i n c l u d e s a n on - b o a rd re f e re nc e an d i n put l o g i c t h a t a c c e pt s t t l, cm os, o r l v p e cl le ve ls. the dig i t a l o u t p u t s log i c le v e l s a r e us er s e lec t ab le as s t anda rd 3 v cm os o r l v ds (ans i-64 4 co m p a t i b le) via p i n s2. enc o de input an y hig h sp e e d a/d con v er t e r i s ext r em e l y s e n s i t i v e t o t h e q u al i t y o f t h e s a m p lin g clo c k p r o v i d e d b y t h e u s er . a t r ack-an d- ho l d c i rc u i t i s e s s e n t i a l l y a m i x e r , an d a n y noi s e, d i s t or t i on , or ti m i n g ji t t e r o n th e c l ock i s co m b in e d wi t h t h e d e si r e d si gn al a t th e a / d o u t p u t . f o r th a t r e a s o n , co n s i d e r a b le ca r e h a s been tak e n in the des i g n o f t h e c l o c k in p u ts o f t h e ad9430, a nd t h e us er is ad vis e d to g i v e ca r e f u l tho u g h t t o t h e c l o c k s o ur ce . the ad9430 has a n in t e r n al c l o c k d u ty c y c l e s t a b iliza t io n cir c ui t tha t lo cks t o the r i sin g e d g e o f clk+ and o p timizes ti m i n g in t e rn ally . t h i s allo ws f o r a w i d e ra n g e o f i n p u t d u t y c y c l es a t th e in p u t wi th o u t de g r adin g per f o r ma n c e. j i t t er in th e r i s i ng e d ge o f t h e in put i s st i l l o f p a ramou n t c o nc er n and is n o t r e d u ced b y th e in t e rnal s t a b iliz a t i o n ci r c ui t . t h e d u t y c y c l e co n t r o l loo p do es n o t f u nc tio n f o r c l o c k ra t e s les s than 30 mh z n o m i n a l l y . t h e lo o p h a s a t i m e con s t a n t ass o c i a t e d w i t h i t t h at n e e d s t o b e c o n s i d e r e d i n ap p l i c at i o n s w h e r e t h e cl o c k r a te c a n change dy namic a l l y , r e q u ir in g a wa i t t i m e o f 1.5 s t o 5 s a f t e r a d y na mic c l o c k f r eq uen c y in cr eas e bef o r e va li d da t a is a v ai la b l e. this c i r c ui t is a l wa y s o n a nd ca n n ot b e dis a b l e d b y t h e us er . the clo c k in pu t s a r e in ter n a l ly b i a s e d t o 1.5 v (n o m in a l ) an d s u p p o r t ei t h er dif f er en t i al o r sing le-e n d e d sig n a l s. f o r b e s t d y na mic p e r f o r ma n c e, a dif f er en t i a l sig n a l is r e co mm e nde d . a n m c 100l vel16 p e r f o r m s w e l l in t h e cir c u i t t o dr i v e t h e c l o c k in p u ts, as il l u s t r a t e d in f i gur e 5 0 . (f o r t r ace len g t h s > 2 in ch es, a st anda r d l v pecl ter m in a t ion is r e co m m e nde d r a t h er t h a n th e si m p le p u ll-d o w n a s sh o w n . ) n o t e tha t f o r th i s lo w v o l t a g e pe c l d e v i c e , t h e a c c o upl i ng i s opt i on a l . pecl ga te 510 ? 510 ? 0.1 f 0.1 f clk ? ad9430 clk+ 02607-050 f i g u re 50. d r iv ing clo c k input s wit h l v e l 16 table 8. out p ut select coding s1 1 s2 1 s4 1 s 5 1 (data format s e lect) (lvds/cmos mode select) 2 (i/p select) (full-scale sele ct) 3 mode 1 x x x twos complement 0 x x x offset binary x 0 1 x dual-mode cmos interleaved x 0 0 x dual-mode cmos paral l el x 1 x x lvds mode x x x 1 full scale = 0.76 8 v x x x 0 full scale = 1.53 6 v 1 x = do nt care . 2 s4 u s e d i n cmos m o de on ly ( s 2 = 0). s1 t o s5 a l l h a ve 30 k?- r esi s t i ve pul l - d own s on - c h i p. 3 s5 ful l - s ca l e a d j u st (se e an a l og in put s sect i o n ) . i n i n te r l e a ve d mo d e , output d a t a o n p o r t a i s of f s e t f r om output d a t a ch ange s on p o r t b b y on e - h a l f output cl o c k c y cl e : interlea ved mode p arallel mode 02607-051 f i g u re 51.
ad9430 rev. c | page 25 of 40 anal og input the ana l og in p u t to t h e a d 94 30 is a dif f er en t i a l b u f f er . f o r b e st d y namic p e r f o r ma n c e, i m p e dan c es a t vi n+ a nd vi n C shou l d m a tch . t h e an a l o g i n put i s opt i m i z e d to pro v i d e sup e r i o r wi deb a nd p e r f o r ma n c e a nd r e q u ir es t h a t t h e a n a l o g in p u ts b e dr i v e n dif f er en t i al l y . s n r and s i n a d p e r f o r ma n c e deg r ades sig n if i c a n t l y if t h e a n a l og in p u t is dr i v en wi t h a s i n g le - ende d sig n a l . a w i deb a nd t r a n sfo r m e r , such as mini -cir c u i t s adt1 -1w t , ca n p r o v i d e t h e dif f er en t i al a n al og in p u ts fo r a pplica t ion s t h a t r e q u ir e a sing le- e nde d - t o - d if fer e n t ia l con v ersion. b o t h a n a l og in p u ts a r e s e lf- b ias e d b y a n o n - c hi p r e sisto r div i der to a n o minal 2.8 v . (s ee t h e e q uival e n t cir c ui ts s e c t io n.) s p e c ia l ca r e was t a k e n in t h e de sig n o f t h e a n a l og in p u t s e c t ion o f th e ad9430 to p r ev en t da mag e a nd co r r u p tio n o f da ta w h en t h e in p u t is o v erdr i v en. th e n o minal dif f er en t i al in p u t ra n g e is a p p r o x ima t e l y 1.5 v p-p ~ (768 mv 2). n o t e t h a t t h e best p e r f o r ma n c e is ac hiev e d wi th s 5 = 0 (f u l l-s c ale = 1.5). s e e f i gur e 43. 2.8v 2.8v vi n + vi n ? 768mv s5 = gnd digit alout = all 1s digit alout = all 0s 02607- 052 f i g u re 52. d i f f e r e nt ia l a n a l og input r a ng e 2.8v s5 = a vdd 768mv vi n + vi n ? = 2.8v 2.8v 02607- 053 f i gure 53. sing le -ended a n alog input range ds in pu t s (ds+, ds C ) i n cmos o u t p u t m o de , t h e da t a syn c in p u ts (d s+, dsC) ca n b e u s e d i n ap p l i c at i o n s t h a t r e q u i r e a g i v e n s a mp l e t o ap p e a r at a s p ecif ic o u t p u t p o r t (a o r b) r e la ti ve t o a g i ven ext e r n al timin g si gn al . th e ds in p u t s ca n also b e used t o sy n c h r o n i z e tw o o r m o r e a d cs in a sys t em t o m a in ta in p h a s i n g b e t w een p o r t s a a nd b o n s e p a r a te ad c s (in ef fe c t , sy n c hr o n i z i n g m u l t i p le d c o o u t p u t s). w h en ds+ is he ld hig h ( d sC l o w), t h e ad c d a t a o u t p u t s and clo c k do n o t s w i t ch and a r e held st a t i c . s y n c hr o n i z a t ion is acco m p li she d b y t h e ass e r t i o n (fa l lin g e d ge ) o f d s + w i t h i n th e ti m i n g c o n s tr a i n t s t sd s and t hd s , r e la t i v e t o a c l o c k r i sin g e d ge . (on ini t ial sy n c hr o n iza t io n, t hd s is n o t r e l e v a n t . ) i f d s + f a ll s w i th i n th e r e q u i r e d se t u p t i m e ( t sd s ) b e fo r e a g i ve n clo c k r i sin g e d ge n, t h e a n a l og va l u e a t t h a t p o i n t in t i me wi l l b e dig i t i ze d and a v a i la b l e a t p o r t a , 14 c y cles la ter in i n te rle a ve d m o de. t h e ve r y ne x t s a m p l e , n + 1 , i s s a m p l e d b y t h e ne x t r i s i ng cl o c k e d g e a n d av a i l a b l e at p o r t b, 1 4 c y c l e s a f t e r t h at c l o c k e d g e . in d u a l p a r a l l el mo de, p o r t a has a 15-c y cle la te nc y a n d p o r t b has a 14-c y cle la te nc y , b u t da t a is a v a i lab l e a t t h e s a m e t i m e . dr iv i n g e a c h a d c s ds in p u ts b y the s a m e sy n c sig n als acco m p lish es t h is. an e a sy w a y t o acco m p lish sy n c hr o n iz a t io n is b y a on e- tim e sy n c a t p o w e r - o n r e s e t. n o t e tha t w h en r u nnin g t h e ad9430 in l v ds mo de , s e t ds+ t o g r o u n d and dsC t o 3.3 v , as th e ds in p u ts a r e r e levan t o n l y in cm os o u t p u t m o de , sim p lif y i n g t h e desig n fo r s o me a p plic a t io n s as w e l l as a f fo r d ing s u pe ri o r s n r / s i n a d pe rf o r m a n c e a t hi g h e r en c o d e /a n a l o g fr e q u e n c i e s . cmos ou tput s the o f f-chi p dr iv ers o n t h e chi p ca n b e co nf igure d t o p r o v ide cm os co m p a t ib le o u t p u t le ve ls v i a p i n s2. the cm os dig i tal o u t p u t s (s2 = 0) a r e t t l/cm os co m p a t i b le f o r lo w e r p o w e r co n s um p t io n. th e o u t p uts a r e b i as e d f r o m a s e p a ra t e s u p p l y ( d r v dd ) , a l l o w i ng e a s y i n te r f a c e to e x te r n a l l o g i c . th e output s a r e cmos de vi ces t h a t s w i n g f r o m g r o u nd to dr vdd ( w i t h n o dc lo ad). i t is r e co mm e nde d to mini mi ze t h e c a p a ci t i ve lo ad t h e ad c dr i v e s b y k e ep in g t h e o u t p u t t r aces sh o r t (< 1 in ch, fo r a tot a l c lo a d < 5 pf). w h en op er a t in g in cmos m o de , i t is a l s o r e co mm e nde d to place lo w v a l u e (20 ? ) s e r i es dam p i n g r e sis t o r s o n the da ta l i n e s t o r e d u ce swi t c h in g tr a n sien t ef fe c t s on p e r f or m a nc e . lv d s o u t p u t s the o f f-chi p dr iv ers o n t h e chi p ca n b e co nf igure d t o p r o v ide l v ds co m p a t i b le o u t p u t le ve ls v i a p i n s2. l v d s o u t p u t s a r e av a i l a b l e w h e n s 2 = v dd a nd a 3.74 k? rs et r e sist o r is place d a t p i n 7 (l vds b i a s) t o g r o u nd . th e rs et r e sis t o r c u r r en t is ra t i o e d on-chi p , s e t t in g t h e o u t p u t c u r r en t a t e a ch o u t p u t e q ual t o a n o mina l 3. 5 ma (11 irs e t). a 100 ? di f f er en ti al t e r m in a t io n r e si st o r place d a t t h e l v ds r e cei v er in p u ts r e su l t s
ad9430 rev. c | page 26 of 40 in a n o minal 35 0 mv s w ing a t t h e r e ceiv er . l v ds mo de faci li t a t e s in t e r f acin g wi t h l v d s r e cei v ers in c u st o m as ics an d fpga s tha t ha ve l v ds ca p a b i l i ty f o r s u p e r i o r swi t c h in g p e r f or m a nc e i n noi s y e n v i ron m e n t s . s i ng l e p o i n t - to - p oi n t ne t t o p o log i es a r e r e co mmen d e d wi th a 100 ? t e r m ina t io n r e sis t o r as clos e t o t h e r e cei v er as p o s s ib le . i t is r e co mm e nde d t o k e ep t h e t r ace len g t h tw o i n ch es maxim u m an d t o k e ep dif f er en t i al o u t p ut t r ace lengt h s as e q ua l as p o ssi b le. cl ock ou t p ut s (dc o + , dc o C ) the i n p u t e n c o de is di v i de d b y tw o (i n cmos m o de) and a v a i la b l e o f f-c h i p a t d c o+ a nd d c oC. th es e c l o c ks can facili t a te la t c hing o f f-c h i p , p r o v idin g a lo w s k e w c l o c kin g s o l u t i o n (s e e f i gur e 2). th e on-chi p clo c k b u f f ers s h o u l d n o t dr i v e m o r e than 5 pf o f ca p a ci t a n c e t o limi t s w i t c h in g tra n sien t ef f e c t s o n p e r f o r ma n c e . n o te t h a t t h e o u t p u t clo c ks a r e cm o s lev e l s w h en cmos m o de is s e le c t ed (s2 = 0) a nd a r e l v ds l e vel s w h e n i n l v d s mo d e ( s 2 = v dd ), (r eq uir i n g a 100 ? dif f er en t i al t e r m ina t io n a t r e c e i v er in l v ds m o de). th e ou t p u t clo c k i n l v ds m o de s w i t ch es a t t h e e n c o d e ra t e . v o l t a g e reference a s t a b l e an d ac c u ra t e 1.23 v v o l t a g e r e fer e n c e is b u i l t in t o t h e ad9430 (vref ) . the a n alog in p u t f u l l -s c a le ran g e is lin e a r l y prop or t i on a l to t h e vo lt age a t v r e f . n o te t h a t a n e x te r n a l re f e re nc e c a n b e u s e d b y c o n n e c t i ng t h e se n s e pi n to v d d (dis a b li n g i n ter n a l r e fer e n c e) and dr ivi n g vre f wi t h t h e ex ter n a l r e fer e nce s o ur ce. n o a p p r e c ia b l e deg r ad a t ion i n p e r f o r ma n c e o c c u rs when v r e f is ad j u s t ed 5 %. a 0.1 f ca p a ci to r to g r o u nd is r e co m m e n de d a t t h e v r ef p i n i n in t e r n a l an d exter n a l r e fer e n c e a p plic a t io n s . flo a t t h e s e ns e p i n fo r in ter n a l r e fer e nc e o p er a t io n. a1 vref 1k ? sense 200 ? 0.1 f disable a1 v dd k full scale + 1v 3.3v external 1.23v reference + + s5 = 0 ? > k = 1.24 s5 = 1 ? > k = 0.62 02607-054 f i gure 54. u s ing an e x tern al r e ference noise po w e r r a tio testing (n pr) npr i s a te s t t h a t i s c o m m on ly u s e d to ch ar a c te r i z e t h e re t u r n p a t h o f cab l e sys t em s w h er e t h e sig n als a r e typ i cal l y q a m sig n als wi th a n o i s e -lik e f r e q uen c y s p e c tr um. np r p e r f o r ma n c e o f th e ad9430 was c h a r ac t e r i zed in t h e l a b yie l din g an ef f e c t i v e np r = 56. 9 db a t an a n alo g in p u t o f 19 mh z. this ag r e es wi t h a t h e o r e t i ca l max i m u m n p r o f 57.1 db f o r a n 11-b i t ad c a t 13 .6 db bac k o f f . th e r m s n o is e po w e r o f t h e s i gn a l i n s i d e th e n o t c h i s c o m p a r ed w i th th e rm s n o is e l e ve l o u tside t h e n o t c h usi n g a n ff t . s u f f i cien t l y lo n g r e co r d len g t h s to gua r a n t e e a s u f f i cien t n u m b er o f s a m p les in sid e t h e n o t c h a r e a r e q u ir e m e n t, as wel l as a h i g h o r der b a nd- s t o p f i l t er t h a t pr o v ides t h e r e q u ir e d n o t c h dept h fo r t e s t in g .
ad9430 rev. c | page 27 of 40 evaluation board, cmos mode the ad9430 evaluation board offers an easy way to test the ad9430 in cmos mode. it requires a clock source, an analog input signal, and a 3.3 v power supply. the clock source is buffered on the board to provide the clocks for the adc, an on- board dac, latches, and a data ready signal. the digital outputs and output clocks are available at two 40-pin connectors, p3 and p4. (see figure 60.) the board has several different modes of operation and is shipped in the following configurations: ? offset binary ? internal voltage reference ? cmos parallel timing ? full-scale adjust = low power connector power is supplied to the board via a detachable 12-lead power strip (three 4-pin blocks). (avdd, drvdd, and vdl are the minimum required power connections). table 9. power connector, cmos mode avdd 3.3 v analog supply for adc (350 ma) drvdd 3.3 v output supply for adc (28 ma) vdl 3.3 v supply for support logic and dac (350 ma) ext_vref optional external reference input vclk/v_xtal supply for clock buffer/optional crystal vamp supply for optional amp analog inputs the evaluation board accepts a 1.3 v p-p analog input signal centered at ground at smb connector j4. this signal is terminated to ground through 50 ? by r16. the input can be alternatively terminated at transformer t1 secondary by r13 and r14. t1 is a wideband rf transformer providing the single- ended-to-differential conversion, allowing the adc to be driven differentially, minimizing even order harmonics. an optional second transformer, t2, can be placed following t1 if desired. this would provide some performance advantage (~1 db to 2 db) for high analog input frequencies (>100 mhz). if t2 is placed, two shorting traces at the pads would need to be cut. the analog signal is low-pass filtered by r41, c12 and r42, c13 at the adc input. gain full scale is set at e17, e18, and e19. connecting e17 to e18 sets s5 low, full scale = 1.5 v differential; connecting e17 to e19 sets s5 high, full scale = 0.75 v differential. encode the encode clock is terminated to ground through 50 at smb connector j5. the input is ac-coupled to a high speed differential receiver (lvel16) that provides the required low jitter, fast edge rates needed for optimum performance. j5 input should be > 0.5 v p-p. power to the el16 is set at jumper e47. connecting e47 to e45 powers the buffer from avdd; connecting e47 to e46 powers the buffer from vclk/v_xtal. voltage reference the ad9430 has an internal 1.23 v voltage reference. the adc uses the internal reference as the default when jumpers e24Ce27 and e25Ce26 are left open. the full scale can be increased by placing optional resistor r3. the required value would vary with the process and needs to be tuned for the specific application. full scale can similarly be reduced by placing r4; tuning is required here as well. an external reference can be used by shorting the sense pin to 3.3 v (place jumper e26Ce25). e27Ce24 jumper connects the adc vref pin to the ext_vref pin at the power connector. data format select data format select sets the output data format of the adc. setting dfs (e1 to e2) low sets the output format to be offset binary; setting dfs high (e1 to e3) sets the output to twos complement. i/p timing select output timing is set at e11, e12 and e13. e12 to e11 sets s4 low for parallel output timing mode. e11 to e13 sets s4 high for interleaved timing mode. timing controls flexibility in latch clocking and output timing is accomplished by allowing for clock inversion at the timing controls section of the pcb. each buffered clock is buffered by an xor and can be inverted by moving the appropriate jumper for that clock. cmos data outputs the adc cmos digital outputs are latched on the board by four lvt574s; the latch outputs are available at the two 40-pin connectors at pins 11C33 on p23 (channel a) and pins 11C33 on p3 (channel b). the latch output clocks (data ready) are available at pin 37 on p23 (channel a) and pin 37 on p3 (channel b). the data-ready clocks can be inverted at the timing controls section if needed
ad9430 rev. c | page 28 of 40 ch1 ch2 ch2 m 5.00ns 1 2 ? 4.6ns c1 freq 84.65608mhz 2.00v 2.00v 02607-055 f i gure 5 5 . d a ta o u tput a n d clo c k @ 80 -p i n c o nnecto r da c o u t p u t s e a ch chan nel is re c o nst r u c te d b y an on- b o a rd, d u a l -chan n el d a c, an ad97 53. this d a c is in t e nde d t o as s i s t in deb u gi t s h o u l d n o t b e u s e d t o m e as ur e t h e p e r f o r ma n c e o f t h e ad c. i t is a c u r r en t o u t p u t d a c wi t h on-bo a r d 50 t e r m ina t ion r e sis t o r s. f i gur e 56 is r e p r es en ta ti v e o f the d a c o u t p u t wi t h a f u l l -s cale a n alog in p u t. the s c op e s e t t i n g is lo w b a ndwi d t h . ch1 ch1 m 25.0ns 1 c1 freq 10.33592mhz c1 p-p 448mv 2.00m ? 248mv 02607-056 f i g u re 56. da c o u t p ut cr y s t a l oscill a t or a n opt i on a l c r y s t a l o s c i l l a tor c a n b e pl a c e d on t h e b o ard to s e r v e as a clo c k s o ur ce fo r t h e p c b . p o w e r t o t h e os ci l l a t o r is t h r o u g h th e v c l k / v x t a l p i n a t th e po w e r c o n n e c t o r . i f a n os ci l l a t o r is us e d , en sur e p r o p e r t e r m ina t io n fo r b e st r e su l t s . the bo a r d has b e en t e st ed wi t h a v a l p ey f i sh er vf561 a nd a v e c t r o n jn0015 8-163.84. t e s t res u l t s f o r th e vf561 a r e s h o w n in f i gur e 57. optio n al a m plifier the f o o t p r in t f o r tra n sf o r m e r t2 ca n be m o dif i ed t o accep t a wideban d dif f er en t i al am p l if ier (ad8350) f o r lo w f r eq uen c y a p plic a t io n s w h er e ga in is r e q u i r e d . n o te t h a t pin 2 w o u l d n e e d t o be l i f t ed and lef t f l o a tin g f o r o p era t ion. i n p u t tra n sf o r m e r t1 wo uld n e e d t o be mo dified t o a 4:1 f o r i m pe da n c e ma t c hin g a n d mhz 0 ?30 08 20 db 40 60 0 ?60 ?80 ?20 ?10 ?50 ?40 ? 100 ?90 ?70 encode 163.84mhz analog 65.02mhz snr 63.93db sinad 63.87db fund ? 0.45dbfs 2nd ?85.62dbc 3rd ?91.31dbc 4th ?90.54dbc 5th ?90.56dbc 6th ?91.12dbc thd ? 82.21dbc sfdr 83.93dbc samples 8k noiseflr ? 100.44dbfs w o rs t s p ? 83. 93d bc 02607-057 f i g u re 57. fft u s i ng v f 56 1 cr yst a l as cl ock s o u r ce ad c i n p u t f i l t e r in g w o u l d en ha n c e p e r f o r ma nce . s e e t h e ad8350 da t a sheet. s n r/s i n a d p e r f o r ma n c e o f 61 db/60 db is p o ssi b le and w o u l d st a r t to deg r ade a t ab o u t 30 mh z. cut tra ce ad8350 1 cut tra ce 02607-058 f i gur e 5 8 . usi n g the ad83 50 o n the a d 9 430 p c b troublesh o o t i n g i f th e boa r d d o es n o t see m t o b e w o r k i n g co rr ec tl y , tr y th e fol l o w ing : ? v e r i f y p o w e r a t i c p i n s . ? c h e c k t h a t al l j u m p ers a r e i n t h e co r r e c t p o si t i o n fo r t h e desir e d m o de o f o p er a t io n . ? v e r i f y tha t vref is a t 1.23 v . ? t r y r u nnin g clo c k an d a n a l o g in p u ts a t lo w sp e e d s (10 ms ps/1 m h z) and m o ni to r la tch, d a c, and ad c fo r t o ggl i n g . the ad9430 eval u a t io n bo a r d is p r o v ided as a desig n exam p l e fo r c u s t o m ers o f analog d e v i ce s, i n c. ad i ma kes n o wa r r a n t i es, exp r es s, s t a t ut o r y , o r im plie d , r e ga r d in g m e r c han t ab i l i t y o r f i t n ess fo r a p a r t ic u l a r p u r p os e.
ad9430 rev. c | page 29 of 40 signal generator signal generator refin 10mhz refout b and-p ass filter analog j4 clock j5 ad9430 evaluation board avdd gnd drvdd gnd vdl gnd 3.3v 3.3v 3.3v + data capture and processing 02607-059 ? + ? + ? f i g u re 59. ev aluat i on b o a r d conn ec t i ons
ad9430 rev. c | page 30 of 40 table 10. evaluation board bill of materialscmos no. quantity reference designator device package value comments 1 47 c1, c3Cc11, c15Cc17, capacitor 0603 0.1 f c43, c47 c19Cc29, c31Cc48, c58Cc62 not placed 2 1 c2 capacitor 0603 10 pf not placed 3 2 c12, c13 capacitor 0603 20 pf not placed 4 1 c14 capacitor 0603 0.01 f 5 1 c18 capacitor 0603 1 f 6 7 c30, c49, c63Cc67 capacitor capl 10 f c30 not placed 7 9 e3, e1, e2 3-pin header/jumper e19, e17, e18 3-pin header/jumper e13, e11, e12 3-pin header/jumper e26, e25, e27, e24 4-pin header e46, e47, e45 3-pin header/jumper e35, e33, e34 3-pin header/jumper e32, e30, e31 3-pin header/jumper e29, e23Ce28 3-pin header/jumper e22, e16Ce21 3-pin header/jumper 8 6 j1, j2, j3, j4, j5, j6 smb smb j2 not placed 9 2 p3, p23 1 10 3 p4, p21, p22 4-pin power connector post z5.531.3425.0 wieland detachable connector 25.602.5453.0 wieland 11 8 r1, r5, r16, r25, r27, r28, resistor 0603 50 ? r1, r13, r14 r41, r42 not placed 12 3 r2, r3, r4 resistor 0603 3.74 k? r3, r4 not placed 13 14 r6Cr8, r10, r15, r21Cr24, resistor 0603 100 ? r15, r21 to r24 r33Cr36, r38 not placed 14 5 r9, r11, r12, r30, r37 resistor 0603 0 ? 15 4 r17, r18, r19, r20 resistor 0603 510 ? 16 1 r26 resistor 0603 2 k ? 17 1 r29 resistor 0603 390 ? 18 7 r31, r32, r39, r40, r43, resistor 0603 1 k ? r44, r45 19 4 rz1, rz2, rz3, rz4 resistor pack 220 w so16res 742c163221jtr cts 20 8 rz5, rz6, rz7, rz8, rz9, resi stor pack 22 w so16res 742c163220jtr cts rz10, rz11, rz12 21 2 t1, t2 transformer cd542 mini-circuits t2 not placed adt1C1wt 22 1 u1 ad9430bsv tqfp100 adc 23 1 u2 mc100lvel16d so8nb clock buffer 24 1 u3 74lvc86 so14nb xor 25 4 u4, u5, u6, u7 74lvt574 so20 latch 26 1 u9 ad9753ast lqfp48 dac 27 2 r13, r14 resistors 0603 25 w r13, r14 not placed 1 p3, p23 are implemented as one physical 80-pin connector samtec tsw-140-08-l-d-ra.
ad9430 rev. c | page 31 of 40 vc c vee dq dn qn vb b gn d e45 e46 vc c vc l k e47 c3 6 0. 1 f j5 gn d r2 7 50 ? c5 0. 1 f e nco de 2 3 4 5 6 7 8 c8 0. 1 f r1 0 510 ? r1 7 510 ? m c 100l vel 16 u2 gn d r2 0 510 ? r1 9 510 ? gn d ou t _ en d0 d1 d2 d3 d4 d5 d6 d7 gn d vc c q0 q1 q2 q3 q4 q5 q6 q7 clo c k l v t 574 u7 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 clkla t b vd l gn d gn d r1 r2 r3 r4 r5 r6 r7 r8 r z 5 22 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dy 4 dy 3 dy 2 dy 1 dy 0 dy a dy b r1 r2 r3 r4 r5 r6 r7 r8 r z 4 220 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ou t _ en d0 d1 d2 d3 d4 d5 d6 d7 gn d vc c q0 q1 q2 q3 q4 q5 q6 q7 clo c k l v t 574 u6 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 clkla t b vd l gn d gn d r1 r2 r3 r4 r5 r6 r7 r8 r z 6 22 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dr y dy 1 1 dy 1 0 dy 9 dy 8 dy 7 dy 6 dy 5 r1 r2 r3 r4 r5 r6 r7 r8 r z 3 220 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c4o m s p3 p40 p38 p36 p34 p32 p30 p28 p26 p24 p22 p20 p18 p16 p14 p12 p10 p8 p6 p4 p2 p39 p37 p35 p33 p31 p29 p27 p25 p23 p21 p19 p17 p15 p13 p11 p9 p7 p5 p3 p1 gn d drb gn d dy 1 1 dy 1 0 dy 9 dy 8 dy 7 dy 6 dy 5 dy 4 dy 3 dy 2 dy 1 dy 0 dy a dy b dr y gn d gn d ou t _ en d0 d1 d2 d3 d4 d5 d6 d7 gn d vc c q0 q1 q2 q3 q4 q5 q6 q7 clo c k l v t 574 u4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 dm8 dm7 dm6 dm5 clkla t a vd l gn d gn d r1 r2 r3 r4 r5 r6 r7 r8 r z 8 22 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 drx dx 1 1 dx 1 0 dx 9 dx 8 dx 7 dx 6 dx 5 r1 r2 r3 r4 r5 r6 r7 r8 r z 1 220 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 c4 o m s p23 p40 p38 p36 p34 p32 p30 p28 p26 p24 p22 p20 p18 p16 p14 p12 p10 p8 p6 p4 p2 p39 p37 p35 p33 p31 p29 p27 p25 p23 p21 p19 p17 p15 p13 p11 p9 p7 p5 p3 p1 gn d dra gn d dx 1 1 dx 1 0 dx 9 dx 8 dx 7 dx 6 dx 5 dx 4 dx 3 dx 2 dx 1 dx 0 dx a dx b drx gn d gn d ou t _ en d0 d1 d2 d3 d4 d5 d6 d7 gn d vc c q0 q1 q2 q3 q4 q5 q6 q7 clo c k l v t 574 u5 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 clkla t a vd l gn d gn d r1 r2 r3 r4 r5 r6 r7 r8 r z 7 22 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 dx 4 dx 3 dx 2 dx 1 dx 0 dx a dx b r1 r2 r3 r4 r5 r6 r7 r8 r z 2 220 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 p1 p2 p3 p4 1 2 3 4 gn d va m p p4 p t mica0 4 p1 p2 p3 p4 1 2 3 4 gn d vd l v c lk/v _ x tal ext _vr e f p21 p t mica0 4 p1 p2 p3 p4 1 2 3 4 gn d av dd ( v cc) gn d drv dd p22 p t mica0 4 e20 vd l e7 drv dd co uta co ut r9 co utab co utb r1 1 h4 mtho le s h3 mtho le s h2 mtho le s h1 mtho le s gn d u3 3 74l vc 86 clklata r3 3 100 ? co uta r1 0 100 ? e35 e34 vc c gn d e33 1 2 u3 6 74l vc 86 dra r3 4 100 ? r8 100 ? e32 e31 vc c gn d e30 4 5 u3 8 74l vc 86 clklatb r3 5 100 ? r7 100 ? e29 e28 vc c gn d e23 9 10 u3 11 74l vc 86 drb r3 6 100 ? r6 100 ? e22 e21 vc c gn d e16 12 13 pl b g n d g r o u nd p ad unde r p art 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 a d 9430 u1 dr v d d gn d gn d co ut co utb dr v d d gn d dr v d d gn d dr v d d gn d gn d vc c vc c gn d gn d vc c vc c gn d gn d gn d vc c vc c vc c gn d gn d gn d dr v d d gn d gn d vc c gn d vc c gn d vc c vc c vc c gn d gn d gn d 0 ? r1 2 c3 0 10 f + c4 0 . 1 f vc c e36 gn d e14 gn d r5 50 ? j1 gn d r1 50 ? j2 j4 analo g 1 5 3 4 2 6 pr i sec r1 6 50 ? c6 0. 1 f t1 adt1 - 1 wt c7 0. 1 f gn d e15 r1 4 29 ? r1 3 25 ? c3 0. 1 f c2 10p f gn d 1 5 3 4 2 6 pr i sec t2 a d t 1-1w t r 1 3 , r1 4 o p t i o n al c4 7 0. 1 f c 11 0. 1 f gn d c4 3 0. 1 f r4 1 25 ? r4 2 25 ? c1 2 20p f gn d t2 opt i on a l gn d c1 3 20p f e1 e3 vc c e2 gn d clk e clk+ gn d vc c gn d gn d vc c vc c gn d gn d vc c vc c gn d gn d gn d vc c e11 e13 vc c e12 gn d e8 e10 vc c e9 gn d r4 0 1k ? gn d e4 e6 vc c e5 gn d r3 9 1k ? gn d c1 0. 1 f gn d e27 e26 vc c e24 ext _vr e f e29 r4 r3 gn d r2 3. 74k ? gn d e17 e19 vc c e18 gn d r3 , r 4 opt i on a l d a t a syn c r1 no t p l ace d c1 0 0. 1 f c9 0. 1 f co uta co utab co utab 02607-060 f i g u re 60. ev aluat i on b o a r d s c h e m a t i c c m os
ad9430 rev. c | page 32 of 40 86 5 12 3 4 opin b opin b gnd gnd in? ou t ? gn d gn d optional amp ad8350 opin opin in+ ou t + enbl v cc gnd vam p u10 + + + gnd vdl gnd dr vdd gnd c64 10 f c16 0.1 f c17 0.1 f c19 0.1 f c21 0.1 f c20 0.1 f c23 0.1 f c22 0.1 f c25 0.1 f c24 0.1 f c27 0.1 f c26 0.1 f c29 0.1 f c28 0.1 f c31 0.1 f c32 0.1 f c35 0.1 f c67 10 f c44 0.1 f c42 0.1 f c41 0.1 f c15 0.1 f c37 0.1 f c65 10 f c61 0.1 f c62 0.1 f c60 0.1 f c59 0.1 f c58 0.1 f c66 10 f c14 0.1 f c63 10 f + c49 10 f c48 0.1 f + vclk gnd vref gnd va m p gnd r23 100 ? gnd gnd r15 100 ? r38 100 ? 1 2 3 e/d nc gnd u8 v cc output b output 6 5 4 vclk vclk gnd r21 100 ? r22 100 ? vclk gnd p1 p2 r38 for vf561 crystal r24 100 ? optional xtal rz12 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 rz10 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 r8 r7 r6 r5 r4 r3 r2 r1 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 dy b dy a dy 0 dy 1 dy 2 dy 3 dy 4 dy 5 dy 6 dy 7 dy 8 dy 9 dy 1 0 dy 1 1 gn d vo l c39 0.1 f gnd dx11 dx10 dx9 dx8 dx7 dx6 dx5 dx4 rz9 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r1 r2 r3 r4 r5 r6 r7 r8 22 dx3 dx2 dx1 dx0 dxa dxb rz11 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 r1 r2 r3 r4 r5 r6 r7 r8 22 1 2 3 4 5 6 11 12 9 10 7 8 vo l c46 0.1 f gnd c45 0.1 f gnd gnd vo l gnd gnd vo l gnd gnd r44 1k ? e4z e40 e41 e39 e37 e38 r45 1k ? 37 38 39 40 41 42 43 44 45 46 47 48 gnd c33 0.1 f r26 2k ? c34 0.1 f gnd vo l gnd r25 50 ? gnd r28 50 ? gnd r30 0 ? vo l gnd c38 0.1 f gnd j3 j6 r37 0 ? gnd r43 1k ? r31 1k ? r32 1k ? gnd vo l dra c40 0.1 f ad9753 r8 r7 r6 r5 r4 r3 r2 r1 r29 392 ? 22 22 c18 1 f gnd v cc u 02607-061 7 f i g u re 61. ev aluat i on b o a r d s c h e m a t i c c m os (c ont i nu ed)
ad9430 rev. c | page 33 of 40 02607-062 f i gure 62. pcb t o p side s ilkscr e en 02607-063 f i gure 63. pcb t o p side cop p er 02607-064 f i gure 64. pcb gro u nd laye r 02607-065 f i g u re 65. pcb spl i t p o wer plan e 02607-066 f i g u r e 6 6 . p c b b o t t o m s i de c o pp er 02607-067 f i g u re 67. pcb bot t o m sid e s ilk s c r e e n
ad9430 rev. c | page 34 of 40 evaluation board, lvds mode the ad9430 evaluation board offers an easy way to test the ad9430 in lvds mode. (the board is also compatible with the ad9411.) it requires a clock source, an analog input signal, and a 3.3 v power supply. the clock source is buffered on the board to provide the clocks for the adc, latches, and a data-ready signal. the digital outputs and output clocks are available at a 40-pin connector, p23. the board has several different modes of operation and is shipped in the following configurations: ? offset binary ? internal voltage reference ? full-scale adjust = low power connector power is supplied to the board via a detachable 8-lead power strip (two 4-pin blocks). note for the following table that vcc, drvdd, and vdl are the minimum required power connections, and lvel16 clock buffer can be powered from vcc or vdl at e47 jumper. table 11. power connector, lvds mode vcc 3.3 v analog supply for adc (350 ma) drvdd 3.3 v output supply for adc (50 ma) vdl 3.3 v supply for support logic ext_vref optional external reference input analog inputs the evaluation board accepts a 1.3 v p-p analog input signal centered at ground at smb connector j4. this signal is terminated to ground through 50 ? by r16. the input can be alternatively terminated at t1 transformer secondary by r13 and r14. t1 is a wideband rf transformer providing the single- ended-to-differential conversion, allowing the adc to be driven differentially, minimizing even-order harmonics. an o ptional second transformer, t2, can be placed following t1 if desired. this provides some performance advantage (~1 C 2db) for high analog input frequencies (>100 mhz). if t2 is placed, two shorting traces at the pads need to be cut. the analog signal can be low-pass filtered by r41, c12 and r42, c13 at the adc input. a wideband differential amplifier (ad8351) can be configured on the pcb for dc-coupled applications. remove c6, c15, c30 to prevent transformer loading of the amp. see the pcb schematic for more information. gain full scale is set at e17Ce19, e17Ce18 sets s5 low, full scale = 1.5 v differential; e17Ce19 sets s5 high, full scale = 0.75 v differential. best performance is obtained at 1.5 v full scale. clock the clock input is terminated to ground through a 50 ? resistor at smb connector j5. the input is ac-coupled to a high speed differential receiver (lvel16) that provides the required low jitter, fast edge rates needed for optimum performance. j5 input should be > 0.5 v p-p. power to the lvel16 is set at jumper e47. e47Ce45 powers the buffer from avdd; e47Ce46 powers the buffer from vclk/v_xtal. voltage reference the ad9430 has an internal 1.23 v voltage reference. the adc uses the internal reference as the default when jumpers e24Ce27 and e25Ce26 are left open. the full scale can be increased by placing optional resistor r3. the required value varies with the process and needs to be tuned for the specific application. full scale can similarly be reduced by placing r4; tuning is required here as well. an external reference can be used by shorting the sense pin to 3.3 v (place jumper e26Ce25). jumper e27Ce24 connects the adc vref pin to the ext_vref pin at the power connector. data format select data format select (dfs) sets the output data format of the adc. setting dfs low (e1Ce2) sets the output format to be offset binary; setting dfs high (e1Ce3) sets the output to twos complement. data outputs the adc lvds digital outputs are routed directly to the connector at the card edge. resistor pads have been placed at the output connector to allow for termination if the connector receiving logic does not have the required differential termination for the data bits and dco. each output trace pair should be terminated differentially at the far end of the line with a single 100 ohm resistor. crystal oscillator an optional crystal oscillator can be placed on the board to serve as a clock source for the pcb. power to the oscillator is through the vclk/vxtal pin at the power connector. if an oscillator is used, ensure proper termination for best results. the board has been tested with a valpey fisher vf561 and a vectron jn00158-163.84.
ad9430 rev. c | page 35 of 40 table 12. evaluation board bill of materiallvds pcb no. quantity reference designator device package value comment 1 33 c1, c4Cc11, c15Cc17, c19Cc32, c35, c36, c58Cc62 c3, c18, c39, c40 capacitors 0603 0.1 f c3, c18, c39, c40 not placed 2 4 c33, c34, c37, c38 capacitor 0402 0.1 f c33, c34, c37, c38 not placed 3 4 c63Cc66 capacitor tajd capl 10 uf 4 1 c2 capacitor 0603 10 pf c2 not placed 5 2 c12, c13 capacitor 0603 20 pf c12, c13 not placed 6 2 j4, j5 jacks smb 7 2 p21, p22 power connectors top 25.602.5453.0 wieland 8 2 p21, p22 power connectors posts z5.531.3425.0 wieland 9 1 p23 40-pin right-angle connector digi-key s2131-20-nd 10 16 r1, r6Cr12, r15, r31Cr37 resistor 0402 100 ? r1, r6Cr12, r15, r31C37 not placed 11 1 r2 resistor 0603 3.8 k? 12 3 r5, r16, r27 resistor 0603 50 ? 13 2 r17, r18 resistor 0603 510 ? 14 2 r19, r20 resistor 0603 150 ? 15 2 r29, r30 resistor 0603 1 k? 16 2 r41, r42 resistor 0603 25 ? 17 2 r3, r4 resistor 0603 3.8 k? 18 2 r13, r14 resistor 0603 25 ? r13, r14 not placed 19 6 r22, r23, r24, r25, r26, r28 resistor 0603 100 ? r22, r23, r24, r25, r26, r28 not placed 20 5 r38, r39, r40, r45, r47 resistor 0402 25 ? r38, r39, r40, r45, r47 not placed 21 2 r43, r44 resistor 0402 10 k? r43, r44 not placed 22 1 r46 resistor 0402 1.2 k? r46 not placed 23 2 r48, r49 resistor 0402 0 ? r48, r49 not placed 24 2 r50, r51 resistor 0402 1 k? r50, r51 not placed 25 1 t1 t2 rf transformer mini circuits adt1-1wt t2 not placed 26 1 u2 rf amp ad8351 27 1 u9 optional crystal oscillator jn00158 or vf561 28 1 u1 ad9430 tqfp-100 29 1 u3 mc100lvel16 so8nb
ad9430 rev. c | page 36 of 40 gnd 40 drb 38 gnd 36 d11b 34 d10b 32 gnd dr gnd d11 d10 39 37 35 33 31 d9b 30 d8b 28 d7b 26 d6b 24 d5b 22 d9 d8 d7 d6 d5 29 27 25 23 21 d4b 20 d3b 18 d2b 16 d1b 14 d0b 12 d4 d3 d2 d1 d0 19 17 15 13 11 d1fb 10 d2fb 8 dorb 6 4 gnd 2 d1f d2f do r gnd 9 7 5 3 1 p40 p38 p36 p34 p32 p30 p28 p26 p24 p22 p20 p18 p16 p14 p12 p10 p8 p6 p4 p2 p39 p37 p35 p33 p31 p29 p27 p25 p23 p21 p19 p17 p15 p13 p11 p9 p7 p5 p3 p1 u1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 r1 100 ? dor dorb r6 100 ? d11 d11b r7 100 ? d10 d10b r8 100 ? d9 d9b r15 100 ? d1 d1b r36 100 ? d0 d0b r35 100 ? d1f d1fb r34 100 ? d2f d2fb r31 100 ? d2 d2b r10 100 ? d6 d6b r37 100 ? dr drb r32 100 ? d3 d3b r11 100 ? d7 d7b r9 100 ? d5 d5b r33 100 ? d4 d4b r12 100 ? d8 d8b gnd vcc vcc gnd gnd vcc vcc gnd gnd gnd vcc vcc vcc gnd gnd drvdd gnd drvdd drvdd drvdd gnd gnd gnd gnd gnd vcc vcc vcc vcc vcc gnd gnd gnd gnd gnd drvdd gnd ~e n c vcc c4 0.1 f gnd gnd r5 50 ? c10 0.1 f c9 0.1 f elout eloutb gnd r19 510 ? r20 510 ? gnd c36 0.1 f vcc vee vbb dn d q qn 2 3 4 5 6 7 8 gnd r18 510 ? r17 510 ? c8 0.1 f vcc e46 e47 vdl e45 10el16 u3 j5 gnd gnd c5 0.1 f encode r27 50 ? c13 20pf gnd gnd vcc gnd gnd vcc vcc gnd gnd vcc vcc gnd gnd gnd vcc c12 20pf c15 0.1 f c3 0.1 f c2 10pf c30 0.1 f c7 0.1 f c1 1 0.1 f c6 0.1 f j4 gnd r16 50 ? r1 4 25 ? r42 25 ? t2 optional gnd gnd r1 3 25 ? gnd ampinb ampin r41 25 ? t1 a d t 1-1wt 1 5 3 4 2 6 t2 a d t 1-1wt 1 5 3 4 2 6 nc nc pri sec pri sec gnd gnd amp analog vcc e19 vcc e3 e17 gnd gnd e18 r30 1k ? vcc r29 1k ? e1 gnd e2 r2 3.8k ? gnd gnd r3 3.8k ? r4 3.8k ? vcc e26 vref e24 e25 e27 gnd c1 0.1 f p16 gnd ground pad under part p1 p2 1 2 gnd vref p3 p4 3 4 gnd vdl p1 p2 1 2 gnd drvdd p3 p4 3 4 gnd vcc p21 ptm1 cro4 p22 ptm1 cro4 h4 mt hol e 6 h3 mt hol e 6 h2 mt hol e 6 h1 mt hol e 6 gnd connector 02607- 068 f i g u re 68. ev aluat i on b o a r d s c h e m a t i cl v ds
ad9430 rev. c | page 37 of 40 02607-069 + c64 10 f c16 0.1 f c17 0.1 f c19 0.1 f c21 0.1 f c20 0.1 f c23 0.1 f c22 0.1 f c25 0.1 f c24 0.1 f c27 0.1 f c26 0.1 f c29 0.1 f c28 0.1 f c31 0.1 f c32 0.1 f c35 0.1 f vcc gnd + c65 10 f c61 0.1 f c62 0.1 f c60 0.1 f c59 0.1 f c58 0.1 f drvdd gnd c66 10 f c18 0.1 f vdl gnd + c63 10 f vref gnd + to use vf561 crystal e/d 1 nc 2 gnd 3 vcc outputb output 6 5 4 jn00158 u9 gnd r28 100 ? r22 100 ? gnd vdl vdl gnd r23 100 ? r25 100 ? vdl gnd r24 100 ? r26 100 ? p4 p5 f i g u re 69. ev aluat i on b o a r d s c h e m a t i cl v ds (cont i nue d ) 02607-070 vdl vdl gnd gnd gnd a mp in amp power down use r43 or r44 u2 ad8351 r44 10k ? r39 25k ? r38 25k ? r40 25k ? r46 1.2k ? r45 25k ? r43 10k ? c33 0.1 f c34 0.1 f vdl gnd gnd r51 1k ? r50 1k ? c38 0.1 f c37 0.1 f r49 0 ? c39 0.1 f r48 0 ? c40 0.1 f ampinb ampin gnd r47 25k ? pwup 1 rgp1 2 inhi 3 inlo 4 rpg2 5 vocm vpos ophi oplo comm 10 9 8 7 6 f i g u re 70. ev aluat i on b o a r d s c h e m a t i cl v ds (cont i nue d )
ad9430 rev. c | page 38 of 40 f 02607-071 f i gure 71. pcb t o p side s ilkscr e en l vds 02607-072 f i gure 72. pcb t o p side cop p er l vd s 02607-073 f i gure 73. pcb gro u nd layerl v ds 02607-074 f i g u re 74. pcb spl i t p o wer plan e l v d s
ad9430 rev. c | page 39 of 40 02607-075 f i g u r e 7 5 . p c b b o t t o m s i de c o pp er l v d s 02607-076 f i g u re 76. pcb bot t o m sid e s ilk s c r e e n l v d s
ad9430 rev. c | page 40 of 40 outline dimensions top view (pins down) 1 25 26 50 76 100 75 51 14.00 sq 16.00 sq 0.27 0.22 0.17 0.50 bsc 1.05 1.00 0.95 0.15 0.05 0.75 0.60 0.45 seating plane 1.20 max 1 25 26 50 76 100 75 51 conductive heat sink 6.50 nom compliant to jedec standards ms-026aed-hd notes 1. center figures are typical unless otherwise noted. 2. the ad9411 has a conductive heat slug to help dissipate heat and ensure reliable operation of the device over the full industrial temperature range. the slug is exposed on the bottom of the package and electrically connected to chip ground. it is recommended that no pcb signal traces or vias be located under the package that could come in contact with the conductive slug. attaching the slug to a ground plane will reduce the junction temperature of the device which may be beneficial in high temperature environments. 7 3.5 0 coplanarity 0.08 0.20 0.09 f i g u re 77. 10 0-l e ad thin q u ad f l at p a ck ag e , e x pos e d p a d [ t qfp/e p ] (sv - 10 0-1) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ption package option ad9430bsv-170 C40c to +85c 100-lead thin quad flat package, exposed pad [tqfp/ep] sv-100-1 ad9430bsvz-17 0 1 C40c to +85c 100-lead thin quad flat package, exposed pad [tqfp/ep] sv-100-1 ad9430bsv-210 C40c to +85c 100-lead thin quad flat package, exposed pad [tqfp/ep] sv-100-1 ad9430bsvz-21 0 1 C40c to +85c 100-lead thin quad flat package, exposed pad [tqfp/ep] sv-100-1 ad9430-cmos/pcb evaluation boar d (c mos mode) shipped with C2 10 grade ad9430-lvds/p cb evaluation boar d (l vds mode ) shipped with C2 10 grade 1 z = pb-fre e part. ? 2004 a n al og d e vic e s , inc . a ll righ t s r e ser v ed . t r a d em arks and r e gist er e d tr adem ar ks ar e t h e proper t y of t h eir respec tiv e o w ners . c02607-0-11/04( c )

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